The present invention is directed, in general, to a semiconductor device and, more specifically, to a semiconductor device having a large topography feature containing small openings located therein to provide improved dielectric thickness control, and a method of manufacture thereof.
One problem currently encountered in today""s semiconductor technology is the inability to inexpensively and accurately planarize a surface of material. While accurate planarization has always been important within the semiconductor manufacturing industry, it has become even more important with the extremely small submicron device sizes associated with present day technologies. As is well known, it is important to achieve effective planarization to conduct a subsequent, accurate, photolithographic process for such submicron feature sizes.
Generally, current semiconductor technology deposits a layer of material, typically a dielectric material such as fluorinated silicon glass (FSG), over features on a semiconductor wafer. Typically, the FSG is deposited using a high density plasma (HDP) process, which has an isotropic etching component associated with it. The isotropic etching component results from the fluorine gas contained in the high density plasma process and the wafer being at an elevated temperature. The high density plasma process is a net deposition process; however, as it is depositing 5 atoms it might be removing 1 atom. The effects of this isotropic component are quite evident across narrow features having a width of less than about 3000 nm, such as interconnects, which are frequently incorporated into today""s integrated circuit designs. This is a result of the narrow features producing. narrow protrusions, and the etching component acting on the sides of the narrow protrusions, and typically converging toward each other and substantially eliminating such protrusions. Even in situations where the sides of the protrusions do not completely converge, if they are narrow enough, they may be easily and effectively planarized with conventional chemical mechanical planarization (CMP) processes. Wide features typically having a width greater than about 3000 nm, such as capacitors, inductors and power buses, are not as advantageously affected by the isotropic etch component of the HDP process, as the narrow features; therefore, the wide features present an entirely different problem.
In certain situations, the dielectric layer is deposited without the fluorine containing gas, therefore no isotropic etching component is present. If the deposition process has an extremely strong physical sputtering component, the protrusions will likewise not form over extremely small features. However, where the isotropic etching component may prevent protrusions over features having a width of about 3000 nm, the strong physical sputtering component is only capable of preventing protrusions over features having a width of about 250 nm. Thus, current semiconductor technologies generally use a process containing an isotropic etching component.
Because the isotropic etch component and the strong physical sputtering component cannot advantageously affect the wide features, as a result of their substantial width, a raised area or anomaly of the deposited material is typically generated above such features. Turning to Prior Art FIG. 1, illustrated is a wide feature 120 and a narrow feature 130 formed over a semiconductor substrate 110. As noticed, when a dielectric material 140 is deposited using a process containing an isotropic etch component or a strong physical sputtering component, a raised area 145 is formed over the wide feature 120 and not over the narrow feature 130. The problem arises when the surface of the dielectric material 140, including the raised area 145, is planarized, typically using a CMP process. Generally, regions containing mainly high areas polish slower than regions containing mostly low areas. This polishing rate differential tends to produce non-uniformity in the material thickness across the chip, which can subsequently affect accuracy, device performance and device yield. Moreover, differences in pattern density between different types of integrated circuits can lead to varying polishing rates, which make manufacturing more difficult and costly.
The semiconductor manufacturing industry, in the past, developed several methods to attempt to minimize pattern density effects during CMP. One method was to alter the various CMP process variables such as down force, carrier speed and polishing pad hardness. Altering the various CMP process variables tends to help; unfortunately, there is a trade-off between within die and across wafer uniformity when these variables are changed. Moreover, the differing variables do not adequately influence the polishing rate. Another method attempted was to deposit xe2x80x9cdummyxe2x80x9d metal features to even out the pattern density. However, its effectiveness depends on the specifics of the circuit layout and the deposition profile of the dielectric material used. Moreover, the xe2x80x9cdummyxe2x80x9d metal technique complicates the circuit design by adding extra capacitance that must be taken into account in predicting performance, which may slow down the circuit in some instances. Other methods were also attempted, but similar to the xe2x80x9cdummyxe2x80x9d metal technique described above, they contained inherent problems.
Accordingly, what is needed in the art is a semiconductor device, including a wide feature, and method of manufacture thereof that takes advantage of the isotropic etch component associated with some present day deposition techniques, and does not experience the problems set forth above with respect to the prior art features.
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device and method of manufacture thereof that provides improved dielectric thickness control. The semiconductor device includes a metal feature located on a semiconductor substrate, wherein the metal feature has openings formed therethrough. The semiconductor device further includes a fluorinated dielectric layer located over the metal feature and within the openings. Thus, the inclusion of openings within the metal feature allows for a substantially planar surface of the fluorinated dielectric layer.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.